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Si 5 32
P R E L I M I N A R Y DA TA S H E E T
DU A L FREQUENCY X O ( 1 0 M H Z T O 1 . 4 GHZ )
Features
Available with any-rate output frequencies from 10 to 945 MHz and selected frequencies to 1.4 GHz Two selectable output frequencies Industry standard 7x5 mm package Available CMOS, LVPECL, LVDS & CML outputs 3.3, 2.5, and 1.8 V supply options 3x better frequency stability than SAW based oscillators 3rd generation DSPLL(R) with superior jitter performance Internal fixed crystal frequency ensures high reliability and low aging Lead-free/RoHS-compliant
Si5602
Applications
SONET/SDH xDSL 10 GbE LAN/WAN Low jitter clock generation Optical modules Test and measurement
Ordering Information: See page 7.
Description
The SI532 dual frequency XO utilizes Silicon Laboratories advanced DSPLL(R) circuitry to provide a very low jitter clock for all output frequencies. The SI532 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional XOs where a different crystal is required for each output frequency, the SI532 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to be optimized for superior frequency, stability, and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments often found in communication systems. The SI532 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, and output format. Specific configurations are factory programmed into the SI532 at the time of shipment, thereby eliminating the long lead times associated with custom oscillators.
Functional Block Diagram
VDD CLK- CLK+
Fixed Frequency XO
Any-rate 10-1400 MHz DSPLL(R) Clock Synthesis
FS
OE
GND
Preliminary Rev. 0.3 12/05
Copyright (c) 2005 by Silicon Laboratories
SI532
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5 32
1. Electrical Specifications
Table 1. SI532 Electrical Specifications
Parameter Min Typ Max Units Notes
Frequency Nominal Frequency LVDS/CML/LVPECL CMOS Initial Accuracy 10 10 -1.5 -20 -50 -- -- -- -- -- -- -- 945 160 1.5 +20 +50 10 Outputs Symmetry RMS Jitter for FOUT > 500 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz RMS Jitter for FOUT of 125 to 500 MHz 12 kHz to 20 MHz Period Jitter for FOUT <160 MHz Peak-to-Peak RMS
LVPECL Output Option mid-level swing (diff) swing (single-ended) LVDS Output Option mid-level swing (diff)
MHz
Specified at time of order by P/N. Also available in bands from 970 to 1134 MHz and 1213 to 1417 MHz. Measured at +25 C at time of shipping Selectable option by P/N. See Section 4. "Ordering Information" on page 7. Frequency drift over projected 15 year life
ppm
Temperature Stability Aging
ppm
ppm
45
--
55
%
LVPECL: LVDS: CMOS:
VDD - 1.3 V (differential) 1.25 V (differential) VDD/2
-- --
0.27 0.30
-- --
ps
FOUT > 500 MHz Differential Modes: LVPECL/LVDS/CML 125 < FOUT < 500 MHz Differential Modes: LVPECL/LVDS/CML Any output N = 1000 cycles
-- -- --
VDD - 1.42 1.1 0.50
0.5 5 1 -- -- --
-- -- --
VDD - 1.25 1.9 0.93
ps ps
V VPP VPP
50 to VDD - 2.0 V
1.125 0.32
1.2 0.40
1.275 0.50
V VPP
Rterm = 100 (differential)
CML Output Option mid-level swing
-- 0.70
VDD - 0.75 0.95
-- 1.20
V VPP
Rterm = 100 (differential)
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Preliminary Rev. 0.3
SI532
Table 1. SI532 Electrical Specifications (Continued)
Parameter
CMOS Output Option VOH VOL
Min
0.8xVDD --
Typ -- --
-- 1
Max
VDD 0.4
Units
V CL = 15 pF
Notes
Rise/Fall time
-- --
350 -- Inputs
ps ns
CML/LVPECL/LVDS at 20% / 80% CMOS with CL = 15 pF
Voltage (VDD) 3.3 V option 2.5 V option 1.8 V option
Current Output enabled TriState mode
2.97 2.25 1.71
-- --
3.3 2.5 1.8
90 60
3.63 2.75 1.89
-- --
V
Optional parameter specified by P/N
mA
Frequency Select (FS) VIH VIL Output Enable VIH VIL
0.75 x VDD 0 0.75 x VDD --
-- -- -- --
VDD 0.5 VDD 0.5
V
FS = "0" selects F0 FS = "1" selects F1
V
Table 2. Absolute Maximum Ratings
Parameter Supply Voltage Storage Temperature Symbol VDD TS Rating -0.5 to +3.8 -55 to +125 Units V C
Preliminary Rev. 0.3
3
Si5 32
Table 3. Environmental Conditions
Parameter Operating Temperature Mechanical Shock Mechanical Vibration Solderability Gross & Fine Leak Resistance to Solvents Conditions/Test Method -40 to +85 C MIL-STD-883F, Method 2002.3 B MIL-STD-883F, Method 2007.3 A MIL-STD-883F, Method 203.8 MIL-STD-883F, Method 1014.7 MIL-STD-883F, Method 2016
Table 4. Pinout
Pin 1 2 3 4 5 6 Symbol FS OE GND CLK+ CLK- (N/A for CMOS) VDD Function Frequency Select Output Enable Ground Oscillator Output Complementary Output (N/C for CMOS) Power Suppy Voltage
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Preliminary Rev. 0.3
SI532
2. Outline Diagram and Suggested Pad Layout
Figure 1 illustrates the package details for the SI532. Table 5 lists the values for the dimensions shown in the illustration.
Figure 1. SI532 Outline Diagram Table 5. Package Diagram Dimensions (mm)
Dimension A b c D D1 e E E1 L S R aaa bbb ccc ddd -- -- -- -- 4.30 1.07 6.10 Min 1.45 1.2 Nom 1.65 1.4 0.60 TYP. 7.00 BSC. 6.2 2.54 BSC. 5.00 BSC. 4.40 1.27 1.815 BSC. 0.7 REF. -- -- -- -- 0.15 0.15 0.10 0.10 4.50 1.47 6.30 Max 1.85 1.6
Preliminary Rev. 0.3
5
Si5 32
3. 6-Pin PCB Land Pattern
Figure 2 illustrates the 6-pin PCB land pattern for the SI532. Table 6 lists the values for the dimensions shown in the illustration.
Figure 2. Si530 PCB Land Pattern Table 6. PCB Land Pattern Dimensions (mm)
Dimension D2 e E2 GD GE VD VE X Y ZD ZE -- -- 0.84 2.00 8.20 REF 7.30 REF 1.70 TYP 2.15 REF 6.78 6.30 Min 5.08 REF 2.54 BSC 4.15 REF -- -- Max
Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm).
6
Preliminary Rev. 0.3
SI532
4. Ordering Information
The SI532 was designed to support a variety of options including frequency, tuning slope, output format, and VDD. Specific device configurations are programmed into the SI532 at time of shipment. A unique part number associated with these options and frequencies will be assigned. The SI532 XO series is supplied in an industrystandard, 7x5 mm package. Part numbers for the SI532 Dual Frequency XO are determined by following configuration tables. Silicon Labs provides a web browser-based part number configuration tool to simplify this process. Refer to www.silabs.com/ VCXO to access this tool and for further ordering instructions.
532
X
X
XXXXXX
B
G
R
Tape & Reel Packaging
532 XO Product Family
Operating Temp Range (C) G -40 to +85C Part Revision Letter Frequency Designator Code Two unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz 970 to 1134 MHz 1213 to 1417 MHz A six digit code will be assigned by SiLabs for the specified combination of frequencies. Note: Six digit codes > 000100 refer to dual XOs programmed with the lower frequency value selected when FS = 0, and the higher value when FS = 1; six digit codes < 000100 refer to dual XOs programmed with the higher frequency value selected when FS = 0, and the lower value when FS = 1. 2 nd Option Code Temp Stability (ppm, max, ) A B 50 20
1 st Option Code A B C D E F G H J K V DD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format LVPECL LVDS CMOS CML LVPECL LVDS CMOS CML CMOS CML
Note: CMOS available to 160 MHz.
Figure 3. Part Number Convention
Preliminary Rev. 0.3
7
Si5 32
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.3
Updated the "Features" section. Updated Table 1, "SI532 Electrical Specifications," on page 2.
Updated LVDS, CML, and CMOS electric specifications.
Updated Figure 1, "SI532 Outline Diagram," on page 5. Updated 4. "Ordering Information" on page 7.
Updated Figure 3, "Part Number Convention," on page 7.
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Preliminary Rev. 0.3
SI532
NOTES:
Preliminary Rev. 0.3
9
Si5 32
CONTACT INFORMATION
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email:VCXOinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.3

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